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FEATURES
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LTC4253 - 48V Hot Swap Controller with Sequencer DESCRIPTIO
The LTC(R)4253 negative voltage Hot SwapTM controller allows a board to be safely inserted and removed from a live backplane. Output current is controlled by three stages of current-limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. The LTC4253 latches off after a circuit fault. Programmable undervoltage and overvoltage detectors disconnect the load whenever the input supply exceeds the desired operating range. The LTC4253's supply input is shunt-regulated, allowing safe operation with very high supply voltages. A multifunction timer delays initial start-up and controls the circuit breaker's response time. The circuit breaker's response time can be accelerated by sensing excessive MOSFET drain voltage, keeping the MOSFET within safe operating area (SOA). A programmable softstart circuit controls MOSFET inrush current at start-up. Three power good outputs are sequenced by a programmable timer to enable external power modules at start-up or disable them if the circuit breaker trips. The LTC4253 is available in 16-pin SSOP.
, LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation.
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Allows Safe Board Insertion and Removal from a Live - 48V Backplane Floating Topology Permits Very High Voltage Operation Programmable Analog Current Limit with Breaker Timer Ideal for Two Battery Feeds Fast Response Time Limits Peak Fault Current Latchoff After Fault Three Sequenced Power Good Outputs Programmable Soft-Start Current Limit Programmable Timer with Drain Voltage Accelerated Response Programmable Undervoltage/Overvoltage Protection Available in a 16-Pin SSOP Package
APPLICATIO S
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Hot Board Insertion Electronic Circuit Breaker - 48V Distributed Power Systems Negative Power Supply Control Central Office Switching Programmable Current Limiting Circuit High Availability Servers Disk Arrays
TYPICAL APPLICATIO
- 48V RTN (LONG PIN)
- 48V/2.5A Hot Swap Controller
VIN CIN 1F R3 100k R4 100k C2 100F R5 100k
RIN 2.8k 16k(1/4W)/6
+
C3 0.1F POWER MODULE 1 EN POWER MODULE 2 EN
- 48V RTN (SHORT PIN)
R1 402k 1%
4 VIN 11 12 5 LTC4253 OV UV RESET PWRGD1 PWRGD2 3 2 EN3 EN2 RD 1M Q1 IRF530S RC 10 CC 18nF RS 0.02 VIN R6 POWER MODULE 1 OUTPUT POWER MODULE 2 OUTPUT R7

RESET R2 32.4k 1%
B3100* - 48V A (LONG PINS) - 48V B B3100*
16 PWRGD3 15 EN3 1 EN2 CSS 68nF 6 10 SS DRAIN 14 9 SQTIMER GATE 13 7 CSQ TIMER SENSE 0.1F VEE C1 10nF CT 0.33F 8
VIN
U
U
U
POWER MODULE 3 EN
4253 TA01
*DIODES, INC. MOC207
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LTC4253
ABSOLUTE
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW EN2 PWRGD2 PWRGD1 VIN RESET SS SENSE VEE 1 2 3 4 5 6 7 8 16 PWRGD3 15 EN3 14 SQTIMER 13 TIMER 12 UV 11 OV 10 DRAIN 9 GATE
(Note 1), All voltages referred to VEE
Current into VIN (100s Pulse) ........................... 100mA Input/Output (Except SENSE and DRAIN) Voltage ...................................- 0.3V to 16V SENSE Voltage ..........................................- 0.6V to 16V Current Out of SENSE Pin (20s Pulse) ............ - 200mA VIN, DRAIN Pin Minimum Voltage ........................ - 0.3V Current into DRAIN Pin (100s Pulse) ................. 20mA Maximum Junction Temperature .......................... 125C Operating Temperature Range LTC4253C ............................................... 0C to 70C LTC4253I ............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC4253CGN LTC4253IGN GN PART MARKING 4253 4253I
GN PACKAGE 16-LEAD PLASTIC SSOP
TJMAX = 125C, JA = 130C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL VZ RZ IIN VLKO VLKH VIH VIL VHYST ILEAK IRESET IEN VSS ISS RSS VCB VACL VFCL VOS VACL + VOS VSS PARAMETER VIN to VEE Zener Voltage VIN to VEE Zener Dynamic Impedance VIN Supply Current VIN Undervoltage Lockout VIN Undervoltage Lockout Hysteresis TTL Input High Voltage TTL Input Low Voltage TTL Input Buffer Hysterisis TTL Input Leakage Current RESET Input Current EN2, EN3 Input Current SS Voltage SS Pin Current SS Output Impedance Circuit Breaker Current Limit Voltage Analog Current Limit Voltage Fast Current Limit Voltage Analog Current Limit Offset Voltage Ratio (VACL + VOS) to SS Voltage VCB = (VSENSE - VEE) VACL = (VSENSE - VEE) VFCL = (VSENSE - VEE)
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS IIN = 2mA IIN = (2mA Thru 30mA) UV/OV = 4V, VIN = (VZ - 0.3V) Coming Out of UVLO (rising VIN)
q q q
MIN 12
TYP 13 5 0.8 9.2 1
MAX 14.5 2 12
UNITS V mA V V V
2 0.8 600 0.1 0.1 120 0.1 2.2 22 28 100 40 80 150 50 100 200 10 0.05 60 120 300 10 10 180 10
Input = 0V VEE VRESET VIN VEN = 4V VEN = 0V After End of SS Timing Cycle UV = OV = 4V, VSENSE = VEE, VSS = 0V (SOURCING) UV= OV = 0V, VSENSE = VEE, VSS = 2V (SINKING)
q q q q
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V mV A A A A V A mA k mV mV mV mV V/V
W
U
U
WW
W
LTC4253
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL IGATE PARAMETER GATE Pin Output Current CONDITIONS UV = OV = 4V, VSENSE = VEE, VGATE = 0V (Sourcing) UV = OV = 4V, VSENSE - VEE = 0.15V, VGATE = 3V (Sinking) UV = OV = 4V, VSENSE - VEE = 0.3V, VGATE = 1V (Sinking) VGATE VGATEL VGATEH VUVHI VUVLO VUVHST VOVHI VOVLO VOVHST ISENSE IINP VTMRH VTMRL ITMR External MOSFET Gate Drive Gate Low Threshold Gate High Threshold UV Pin Threshold HIGH UV Pin Threshold LOW UV Pin Hysteresis OV Pin Threshold HIGH OV Pin Threshold LOW OV Pin Hysteresis SENSE Pin Input Current UV,OV Pin Input Current TIMER Pin Voltage High Threshold TIMER Pin Voltage Low Threshold TIMER Pin Current Timer On (Initial Cycle/Latchoff, Sourcing), VTMR = 2V Timer Off (Initial Cycle, Sinking), VTMR = 2V Timer On (Circuit Breaker, Sourcing, IDRN = 0A), VTMR = 2V Timer On (Circuit Breaker, Sourcing, IDRN = 50A), VTMR = 2V Timer Off (Circuit Breaker, Sinking), VTMR = 2V ITMRACC IDRN VSQTMRH VSQTMRL ISQTMR (ITMR at IDRN = 50A - ITMR at IDRN = 0A) 50A SQTIMER Pin Voltage High Threshold SQTIMER Pin Voltage Low Threshold SQTIMER Pin Current SQTIMER On (Power Good Sequence, Sourcing), VSQTMR = 2V SQTIMER On (Power Good Sequence, Sinking), VSQTMR = 2V VDRNL IDRNL VDRNCL VPGL IPGH DRAIN Pin Voltage Low Threshold DRAIN Leakage Current DRAIN Pin Clamp Voltage PWRGD1, PWRGD2, PWRGD3 Output Low Voltage PWRGD1, PWRGD2, PWRGD3 Output High Current For PWRGD1, PWRGD2, PWRGD3 Status VDRAIN = 5V IDRN = 50A IPG = 1.6mA IPG = 5mA VPG = 0V
q q q q q q
ELECTRICAL CHARACTERISTICS
MIN 30
TYP 50 17 190
MAX 70
UNITS A mA mA
VGATE - VEE, IIN = 2mA (Before Gate Ramp Up) VGATEH = VIN - VGATE, For PWRGD1, PWRGD2, PWRGD3 Status
q
10
12 0.5 2.8
VZ
V V V
q q
3.075 2.775 0.23 5.85 5.55 0.23 - 30
3.225 2.925 0.3 6.15 5.85 0.3 -15 0.1 4 1 5 28 200 600 5 8 4 0.33 5 28 2.385 0.1 7 0.25
3.375 3.075 0.35 6.45 6.15 0.35 1
V V V V V V A A V V A mA A A A A/A V V A mA V
UV = 0V = 4V, VSENSE = 50mV UV = OV = 4V
q q
Timer On (Circuit Breaker with IDRN = 50A)
1 0.4 1.2 70
A V V V A
30
50
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LTC4253
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2)
SYMBOL tSQ tSS tPLLUG tPHLOG PARAMETER SQTIMER Default Ramp Period SS Default Ramp Period UV Low to GATE Low OV High to GATE Low CONDITIONS SQTIMER Pin Floating, VSQTMR Ramps from 0.5V to 3.5V SS Pin Floating, VSS Ramps from 0.2V to 2V MIN TYP 250 250 0.4 0.4 MAX UNITS s s s s
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified.
TYPICAL PERFOR A CE CHARACTERISTICS
rZ vs Temperature
10 9 8 7 IIN = 2mA 14.0
100 TA = -40C TA = 85C TA = 125C
6 5 4
IIN (mA)
rZ ()
VZ (V)
3 2 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G01
IIN vs Temperature
1000 950 900 10.0 850
VLKO (V)
VIN = VZ - 0.3V
VLKH (V)
IIN (A)
800 750 700 650
600 550 500 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G04
4
UW
VZ vs Temperature
14.5 IIN = 2mA
1000
IIN vs VIN
13.5
TA = 25C 10
13.0
12.5
1
12.0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G02
0.1
0
5
10 VIN (V)
15
20
4253 G03
Undervoltage Lockout VLKO vs Temperature
11.0 10.5 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G05
Undervoltage Lockout Hysterisis VLKH vs Temperature
9.5 9.0 8.5 8.0 7.5 7.0 -55 -35 -15
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G06
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LTC4253 TYPICAL PERFOR A CE CHARACTERISTICS
VIH vs Temperature
4.0 3.5 3.0 1.4
VHYST (V)
IIN = 2mA
2.5
VIH (V)
2.0 1.5 1.0
VIL (V)
0.5 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G07
IEN vs VEN
180 160 140 120 IIN = 2mA TA = 25C 150 145 140 135
100 80 60 40 20 0 0 2 4 6 8 10 VEN (V) 12 14 16
125 120 115 110 105 100 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G11
VCB (mV)
IEN (A)
IEN (A)
Analog Current Limit Voltage VACL vs Temperature
150 140 130 120
VACL (mV) VFCL (mV)
VSS (V)
110 100 90 80 70 60 50 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G13
UW
4253 G10
VIL vs Temperature
2.0 1.8 1.6 IIN = 2mA 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G08
VHYST vs Temperature
IIN = 2mA
1.2 1.0 0.8 0.6 0.4 0.2 0 -55 -35 -15
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G09
IEN (VEN = 4V) vs Temperature
55 IIN = 2mA VEN = 4V 54 53 52 51 50 49 48 47 46
Circuit Breaker Current Limit Voltage VCB vs Temperature
130
45 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G12
Fast Current Limit Voltage VFCL vs Temperature
300 280 260 2.30 240 220 200 180 160 2.10 140 120 100 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G14
VSS vs Temperature
2.40 2.35
2.25 2.20 2.15
2.05 2.00 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G15
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LTC4253 TYPICAL PERFOR A CE CHARACTERISTICS
ISS (Sinking) vs Temperature
50 45 40 35 UV/OV = 0V VSENSE = VEE VSS = 2V IIN = 2mA
RSS (k)
25 20 15 10 5 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G16
100 95 90 85 80 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G17
VOS (mV)
ISS (mA)
30
(VACL + VOS) / VSS vs Temperature
0.060 0.058 0.056 60 58 56 54 IGATE (A) 52 50 48 46 44 42 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G19
(VACL + VOS)/VSS (V/V)
0.054 0.052 0.050 0.048 0.046 0.044 0.042 0.040 -55 -35 -15
IGATE (mA)
IGATE (FCL, Sink) vs Temperature
400 350 300 IGATE (mA) 250 200 150 100 50 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G22
UV/OV = 4V TIMER = 0V VSENSE - VEE = 0.3V VGATE = 1V
12.5 12.0 11.5 11.0 10.5 10.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G23
VGATEL (V)
VGATE (V)
6
UW
RSS vs Temperature
120 115 110 105 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2
VOS vs Temperature
9.0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G18
IGATE (Source) vs Temperature
30 UV/OV = 4V TIMER = 0V VSENSE = VEE VGATE = 0V 25 20 15 10 5
IGATE (ACL, Sink) vs Temperature
UV/OV = 4V TIMER = 0V VSENSE - VEE = 0.15V VGATE = 3V
40 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G20
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G21
VGATE vs Temperature
14.5 14.0 13.5 13.0 UV/OV = 4V TIMER = 0V VSENSE = VEE IIN = 2mA 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
VGATEL vs Temperature
UV/OV = 4V TIMER = 0V GATE THRESHOLD BEFORE RAMP UP
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G24
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LTC4253 TYPICAL PERFOR A CE CHARACTERISTICS
VGATEH vs Temperature
3.6 3.4 3.2 VGATEH (V) 3.0 2.8 2.6 2.4 2.2 2.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G25
UV/OV = 4V VGATEH = VIN - VGATE IIN = 2mA
UV THRESHOLD (V)
OV THRESHOLD (V)
ISENSE vs ( VSENSE - VEE )
0.01
0 -5 -10
0.1 -ISENSE (mA)
TIMER THRESHOLD (V)
ISENSE (A)
1
10 UV/OV = 4V TIMER = 0V GATE = HIGH TA = 25C -1 -0.5 0 0.5 VSENSE - VEE (V) 1 1.5
4253 G28
100
1000 -1.5
ITMR (Initial Cycle, Sourcing) vs Temperature
10 9 8 7 ITMR (mA) ITMR (A) 6 5 4 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G31
IIN = 2mA VTMR = 2V
ITMR (A)
UW
UV Threshold vs Temperature
3.375 IIN = 2mA 3.275 VUVH 3.175 3.075 2.975 VUVL 2.875 2.775 -55 -35 -15 6.45 6.35 6.25 6.15 6.05 5.95 5.85 5.75 5.65 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G26
OV Threshold vs Temperature
IIN = 2mA
VOVH
VOVH
5.55 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G27
ISENSE vs Temperature
5.0
UV/OV = 4V TIMER = 0V VSENSE - VEE = 50mV VGATE = HIGH
TIMER Threshold vs Temperature
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VTMRL IIN = 2mA VTMRH
-15 -20 -25 -30 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G29
0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G30
ITMR (Initial Cycle, Sinking) vs Temperature
50 45 40 35 30 25 20 15 180 10 5 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G32
ITMR (Circuit Breaker, Sourcing) vs Temperature
240 230 220 210 200 190 IIN = 2mA IDRN = 0A
IIN = 2mA VTMR = 2V
170 160 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G33
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LTC4253 TYPICAL PERFOR A CE CHARACTERISTICS
ITMR (Circuit Breaker, Sinking) vs Temperature
10 9 8 7 ITMR (A) ITMR (A) 6 5 4 3 2 1 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G34
IIN = 2mA 675 650
ITMR (mA)
ITMRACC/IDRN vs Temperature
9.0 8.8 8.6 ITMRACC/IDRN (A/A) 8.4 VSQTMR (V) 8.2 8.0 7.8 7.6 7.4 7.2 7.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G37
IIN = 2mA
3.0 2.5 2.0 1.5 1.0 0.5 0 -55 -35 -15 VSQTMRL
ISQTMR (A)
ISQTMR (Power Good Sequence, Sinking) vs Temperature
50 45 40 35 ISQTMR (mA) IIN = 2mA VSQTMR = 2V 2.60 2.55 2.50
25 20 15 10 5 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G40
2.40 2.35 2.30
VDRNCL (V)
VDRNL (V)
30
8
UW
ITMR (Circuit Breaker, IDRN = 50A, Sourcing) vs Temperature
700 IIN = 2mA IDRN = 50A 10
ITMR vs IDRN
IIN = 2mA TA = 25C
625 600 575 550 -55 -35 -15
1
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G35
0.1 0.001
0.01
0.1 IDRN (mA)
1
10
4253 G36
SQTIMER Threshold vs Temperature
5.0 4.5 4.0 3.5 IIN = 2mA VSQTMRH 6.0 5.8 5.6 5.4 5.2 5.0 4.8 4.6 4.4 4.2
ISQTMR (Power Good Sequence, Sourcing) vs Temperature
IIN = 2mA VSQTMR = 2V
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G38
4.0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G39
VDRNL vs Temperature
8.0 IIN = 2mA 7.8 7.6 7.4 2.45 7.2 7.0 6.8 6.6 6.4 2.25 2.20 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G41
VDRNCL vs Temperature
IIN = 2mA IDRN = 50A
6.2 6.0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G42
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LTC4253 TYPICAL PERFOR A CE CHARACTERISTICS
IDRN vs VDRAIN
100 IIN = 2mA 10 1 2.0 2.5 IPG = 10mA
VPGH (A)
IDRN (mA)
VPGL (V)
0.1 TA = 85C 0.01 0.001 TA = 125C
0.0001 0.00001 0 2 TA = -40C 4 6
TA = 25C 10 VDRAIN (V) 8 12 14 16
4253 G43
tSS vs Temperature
300 290 280 270 IIN = 2mA SS PIN FLOATING VSS RAMPS FROM 0.2V TO 2V 500 450 400 350
250 240 230 220 210 200 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G46
tSQ (s)
tSS (s)
260
300 250 200 150 100 50 0 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G47
DELAY (s)
UW
VPGL vs Temperature
3.0 IIN = 2mA 60 58 56 54 52 50 48 46 IPG = 1.6mA 44 42
IPGH vs Temperature
IIN = 2mA VPWRGD = 0V
1.5 IPG = 5mA 1.0 0.5 0 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G44
40 -55 -35 -15
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G45
tSQ vs Temperature
0.6 IIN = 2mA VSQTMR RAMPS FROM 0.5V TO 3.5V
tPLLUG and tPHLOG vs Temperature
IIN = 2mA 0.5 tPLLUG 0.4 0.3 0.2 0.1 0 -55 -35 -15 tPLLOG
5 25 45 65 85 105 125 TEMPERATURE (C)
4253 G48
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LTC4253
PI FU CTIO S
EN2 (Pin 1): Power Good Status Output Two Enable. This is a TTL compatible input that is used to control PWRGD2 and PWRGD3 outputs. When EN2 is driven low, both PWRGD2 and PWRGD3 will go high. When EN2 is driven high, PWRGD2 will go low provided PWRGD1 has been active for more than one power good sequence delay (tSQT) provided by the sequencing timer. EN2 can be used to control the power good sequence. This pin is internally pulled low by a 120A current source. PWRGD2 (Pin 2): Power Good Status Output Two. Power good sequence starts with PWRGD1 latching active low. PWRGD2 will latch active low after EN2 goes high and after one power good sequence delay tSQT provided by the sequencing timer from the time PWRGD1 goes low, whichever comes later. PWRGD2 is reset by PWRGD1 going high or EN2 going low. This pin is internally pulled high by a 50A current source. PWRGD1 (Pin 3): Power Good Status Output One. At start-up, PWRGD1 latches active low and starts the power good sequence when the DRAIN pin is below 2.385V and GATE is within 2.8V of VIN. PWRGD1 status is reset by UV, VIN (UVLO), RESET going high or circuit breaker fault time-out. This pin is internally pulled high by a 50A current source. VIN (Pin 4): Positive Supply Input. Connect this pin to the positive side of the supply through a dropping resistor. A shunt regulator clamps VIN at 13V above VEE. An internal undervoltage lockout (UVLO) circuit holds GATE low until the VIN pin is greater than VLKO (9.2V), overriding UV and OV. If UV is high, OV is low and VIN comes out of UVLO, TIMER starts an initial timing cycle before initiating GATE ramp up. If VIN drops below approximately 8.2V, GATE pulls low immediately. RESET (Pin 5): Circuit Breaker Reset Pin. This is an asynchronous TTL compatible input. RESET going high will pull GATE, SS, TIMER, SQTIMER low and the PWRGD outputs high. The RESET pulse must be wide enough to discharge any voltage on the TIMER pin below VTMRL. After the reset of a latched fault, the chip waits for the interlock conditions before recovering as described in Interlock Conditions in the Operation section. SS (Pin 6): Soft-Start Pin. This pin is used to ramp inrush current during start up, thereby effecting control over di/dt. A 20X attenuated version of the SS pin voltage is presented to the current limit amplifier. This attenuated voltage limits the MOSFET's drain current through the sense resistor during the soft-start current limiting. At the beginning of the start-up cycle, the SS capacitor (CSS) is ramped by a 22A current source. The GATE pin is held low until SS exceeds 20 * VOS = 0.2V. SS is internally shunted by 100k RSS which limits the SS pin voltage to 2.2V. This corresponds to an analog current limit SENSE voltage of 100mV. If the SS capacitor is omitted, the SS pin ramps from 0V to 2.2V in about 250s. The SS pin is pulled low under any of the following conditions: UVLO at VIN, UV, OV, during the initial timing cycle, a circuit breaker fault time-out or the RESET pin going high. SENSE (Pin 7): Circuit Breaker/Current Limit Sense Pin. Load current is monitored by a sense resistor RS connected between SENSE and VEE, and controlled in three steps. If SENSE exceeds VCB (50mV), the circuit breaker comparator activates a (200A + 8 * IDRN) TIMER pull-up current. If SENSE exceeds VACL (100mV), the analog current-limit amplifier pulls GATE down to regulate the MOSFET current at VACL/RS. In the event of a catastrophic short-circuit, SENSE may overshoot 100mV. If SENSE reaches VFCL (200mV), the fast current-limit comparator pulls GATE low with a strong pull-down. To disable the circuit breaker and current limit functions, connect SENSE to VEE. VEE (Pin 8): Negative Supply Voltage Input. Connect this pin to the negative side of the power supply. GATE (Pin 9): N-channel MOSFET Gate Drive Output. This pin is pulled high by a 50A current source. GATE is pulled low by invalid conditions at VIN (UVLO), UV, OV, during the initial timing cycle, a circuit breaker fault time-out or the
10
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U
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LTC4253
PI FU CTIO S
RESET pin going high. GATE is actively servoed to control the fault current as measured at SENSE. Compensation capacitor, CC, at GATE stabilizes this loop. A comparator monitors GATE to ensure that it is low before allowing an initial timing cycle, GATE ramp up after an overvoltage event or restart after a current limit fault. During GATE start-up, a second comparator detects GATE within 2.8V of VIN before PWRGD1 can be set and power good sequencing starts. DRAIN (Pin 10): Drain Sense Input. Connecting an external resistor, RD between this pin and the MOSFET's drain (VOUT) allows voltage sensing below 6.15V and current feedback to TIMER. A comparator detects if DRAIN is below 2.385V and together with the GATE high comparator, sets the PWRGD1 flag. If VOUT is above VDRNCL, the DRAIN pin is clamped at approximately VDRNCL. RD current is internally multiplied by 8 and added to TIMER's 200A during a circuit breaker fault cycle. This reduces the fault time and MOSFET heating. OV (Pin 11): Over-Voltage Input. The active high threshold at the OV pin is set at 6.15V with 0.3V hysteresis. If OV > 6.15V, GATE pulls low. When OV returns below 5.85V, GATE start-up begins without an initial timing cycle. If OV occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after OV goes away. OV does not reset the latched fault or PWRGD1 flag. The internal UVLO at VIN always overrides OV. A 1nF to 10nF capacitor at OV prevents transients and switching noise from affecting the OV thresholds and prevents glitches at the GATE. UV (Pin 12): Under-Voltage Input. The active low threshold at the UV pin is set at 2.925V with 0.3V hysteresis. If UV < 2.925V, PWRGD1 pulls high, both GATE and TIMER pull low. If UV rises above 3.225V, this initiates an initial timing cycle followed by GATE start-up. The internal UVLO at VIN always overrides UV. A low at UV resets an internal fault latch. A 1nF to 10nF capacitor at UV prevents transients and switching noise from affecting the UV thresholds and prevents glitches at the GATE pin. TIMER (Pin 13): Timer Input. Timer is used to generate an initial timing delay at start-up, and to delay shutdown in the event of an output overload (circuit breaker fault). Timer starts an initial timing cycle when the following conditions are met: RESET is low, UV is high, OV is low, VIN clears UVLO, TIMER pin is low, GATE pin is lower than VGATEL, SS < 0.2V, and VSENSE-VEE < VCB. A pull-up current of 5A then charges CT, generating a time delay. If CT charges to VTMRH (4V), the timing cycle terminates. TIMER quickly pulls low and GATE is activated. If SENSE exceeds 50mV while GATE is high, a circuit breaker cycle begins with a 200A pull-up current charging CT. If DRAIN is approximately 7V during this cycle, the timer pull-up has an additional current of 8 * IDRN. If SENSE drops below 50mV before TIMER reaches 4V, a 5A pulldown current slowly discharges the CT. In the event that CT eventually integrates up to the VTMRH (4V) threshold, the circuit breaker trips, GATE quickly pulls low and the PWRGD1 pulls high. TIMER latches high with a 5A pullup source. This latched fault may be cleared by driving RESET high until TIMER is pulled low. Other ways of clearing the fault include pulling the VIN pin momentarily below (VLKO - VLKH), pulling TIMER low with an external device or pulling UV below 2.925V. SQTIMER (Pin 14): Sequencing Timer Input. The sequencing timer provides a delay tSQT for the power good sequencing. This delay is programmed by connecting an appropriate capacitor to this pin. If the SQTIMER capacitor is omitted, the SQTIMER pin ramps from 0V to 4V in about 300s. EN3 (Pin 15): Power Good Status Output Three Enable. This is a TTL compatible input that is used to control the PWRGD3 output. When EN3 is driven low, PWRGD3 will go high. When EN3 is driven high, PWRGD3 will go low provided PWRGD2 has been active for for more than one power good sequence delay (tSQT). EN3 can be used to control the power good sequence. This pin is internally pulled low by a 120A current source. PWRGD3 (Pin 16): Power Good Status Output Three. Power good sequence starts with PWRGD1 latching active low. PWRGD3 will latch active low after EN3 goes high and after one power good sequence delay tSQT provided by the sequencing timer from the time PWRGD2 goes low, whichever comes later. PWRGD3 is reset by PWRGD1 going high or EN3 going low. This pin is internally pulled high by a 50A current source.
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LTC4253
BLOCK DIAGRA
VIN 50A PWRGD1 3 VEE VIN 4 VIN
VEE EN2 1 VIN 120A 50A PWRGD2 2 SQTIMER DELAY VEE EN3 15 VIN 120A 50A PWRGD3 16 SQTIMER DELAY VEE VEE VIN 50A VEE VEE
OV 11
UV 12
VIN 200A
TIMER 13
VEE VIN 22A VEE
SS 6 10mV 95k RSS 5k VEE VEE CB
12
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- +
14 SQTIMER 4V 5A
- + -
VIN 0.33V VEE
10 DRAIN
+
2.385V
8x
1x
6.15V
1x
1x
9 GATE VIN VEE
6.15V
- +
- +
+ -
2.8V
-
2.925V VIN 5A 4V
-
LOGIC
+
+
0.5V
-
FCL
+ - + -
200mV
+
-
5A 1V
VEE
+ +
ACL
- + -
VEE
+ - + -
VEE 5 RESET 8 VEE 50mV
7 SENSE
4253 BD
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LTC4253
OPERATIO
Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient currents from the power bus as they charge. The flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. The LTC4253 is designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. Initial Start-Up The LTC4253 resides on a removable circuit board and controls the path between the connector and load or
-48RTN
***
SHORT R1 402k 1% CIN 1F
***
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power conversion circuitry with an external MOSFET switch (see Figure 1). Both inrush control and short-circuit protection are provided by the MOSFET. A detailed schematic is shown in Figure 2. - 48V and - 48RTN receive power through the longest connector pins and are the first to connect when the board is inserted. The GATE pin holds the MOSFET off during this time. UV/OV determines whether or not the MOSFET should be turned on based upon internal high accuracy thresholds and an external divider. UV/OV does double duty by also monitoring whether or not the connector is seated. The top of the divider detects - 48RTN by way of a short connector pin that is the last to mate during the insertion sequence.
PLUG-IN BOARD -48RTN LTC4253
+ +
CLOAD
+
LOW VOLTAGE CIRCUITRY
ISOLATED DC/DC CONVERTER MODULE
-48V BACKPLANE
-
-
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Figure 1. Basic LTC4253 Hot Swap Topology
LONG RIN 10k 20k(1/4W)/2 4 VIN 11, 12 13 C1 10nF CT 0.33F CSQ 0.1F R2 32.4k 1% LONG -48V RS 0.02 Q1 IRF530S
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1 LTC4253
15
EN2 EN3 PWRGD1 PWRGD2 PWRGD3 RESET DRAIN SENSE 7 CC 18nF RC 10 GATE 9 RD 1M 3 2 16 5 10 *** *** ***
CLOAD 100F TYP
OV/UV TIMER
14
SQTIMER 6 SS VEE 8
CSS 68nF
Figure 2. - 48V/2.5A Hot Swap Controller
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LTC4253
OPERATIO
Interlock Conditions A start-up sequence commences once these "interlock" conditions are met: 1. The input voltage VIN exceeds 9.2V (UVLO). 2. The voltage at UV > 3.225V. 3. The voltage at OV < 5.85V. 4. The input voltage at RESET < 0.8V. 5. The (SENSE - VEE ) voltage < 50mV (VCB) 6. The voltage at SS is < 0.2V (20 * VOS) 7. The voltage on the TIMER capacitor ( CT ) is < 1V (VTMRL). 8. The voltage at GATE is < 0.5V (VGATEL) The first four conditions are continuously monitored and the latter four are checked prior to initial timing or GATE ramp-up. Upon exiting an OV condition, the TIMER pin voltage requirement is inhibited. Details are described in the Applications Information, Timing Waveforms section. TIMER begins the start-up sequence by sourcing 5A into CT. If VIN, UV or OV falls out of range or RESET asserts, the start-up cycle stops and TIMER discharges CT to less than 1V, then waits until the aforementioned conditions are once again met. If CT successfully charges to 4V, TIMER pulls low and both SS and GATE pins are released. GATE sources 50A (IGATE), charging the MOSFET gate and associated capacitance. The SS voltage ramp limits VSENSE to control the inrush current. PWRGD1 pulls active low when GATE is within 2.8V of VIN and DRAIN is lower than VDRNL. This sets off the power good sequence in which PWRGD2 and then PWRGD3 is subsequently pulled low after a delay, programmable through the SQTIMER capacitor CSQ or by external control inputs EN2 and EN3. In this way, external loads or power modules controlled by the three PWRGD signals are turned on in a controlled manner without overloading the power bus. Two modes of operation are possible during the time the MOSFET is first turned on, depending on the values of external components, MOSFET characteristics and nominal design current. One possibility is that the MOSFET will turn on gradually so that the inrush into the load capacitance
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remains a low value. The output will simply ramp to - 48V and the LTC4253 will fully enhance the MOSFET. A second possibility is that the load current exceeds the soft-start current limit threshold of [VSS(t)/20 - VOS]/RS. In this case the LTC4253 will ramp the output by sourcing soft-start limited current into the load capacitance. If the soft-start voltage is below 1.2V, the circuit breaker TIMER is held low. Above 1.2V, TIMER ramps up. It is important to set the timer delay so that, regardless of which start-up mode is used, the TIMER ramp is less than one circuit breaker delay time. If this condition is not met, the LTC4253 may shut down after one circuit breaker delay time. Board Removal When the board is withdrawn from the card cage, the UV/OV divider is the first to lose connection. This shuts off the MOSFET and commutates the flow of current in the connector. When the power pins subsequently separate there is no arcing. Current Control Three levels of protection handle short-circuit and overload conditions. Load current is monitored by SENSE and resistor RS. There are three distinct thresholds at SENSE: 50mV for a timed circuit breaker function; 100mV for an analog current limit loop; and 200mV for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. If, due to an output overload, the voltage drop across RS exceeds 50mV, TIMER sources 200A into CT. CT eventually charges to a 4V threshold and the LTC4253 shuts off. If the overload goes away before CT reaches 4V and SENSE measures less than 50mV, CT slowly discharges (5A). In this way the LTC4253's circuit breaker function responds to low duty cycle overloads, and accounts for the fast heating and slow cooling characteristic of the MOSFET. Higher overloads are handled by an analog current limit loop. If the drop across RS reaches 100mV, the current limiting loop servos the MOSFET gate and maintains a constant output current of 100mV/RS. In current limit mode, VOUT (MOSFET drain-source voltage drop) typically rises and this increases MOSFET heating. If VOUT > VDRNCL (7V), connecting an external resistor, RD between VOUT
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LTC4253
OPERATIO
and DRAIN allows the fault timing cycle to be shortened by accelerating the charging of the TIMER capacitor. The TIMER pull-up current is increased by 8 * IDRN. Note that because SENSE > 50mV, TIMER charges CT during this time, and the LTC4253 will eventually shut down. Low impedance failures on the load side of the LTC4253 coupled with 48V or more driving potential can produce current slew rates well in excess of 50A/s. Under these conditions, overshoot is inevitable. A fast SENSE comparator with a threshold of 200mV detects overshoot and pulls GATE low much harder and hence much faster than the weaker current limit loop. The 100mV/RS current limit loop then takes over, and servos the current as previously described. As before, TIMER runs and shuts down LTC4253 when CT reaches 4V. If CT reaches 4V, the LTC4253 latches off with a 5A pullup current source. The LTC4253 circuit breaker latch is
APPLICATIO S I FOR ATIO
SHUNT REGULATOR
A fast responding regulator shunts the LTC4253 VIN pin. Power is derived from -48RTN by an external current limiting resistor. The shunt regulator clamps VIN to 13V (VZ). A 1F decoupling capacitor at VIN filters supply transients and contributes a short delay at start-up. RIN should be chosen to accommodate both VIN supply current and the drive required for three optocouplers used by the PWRGD signals. Higher current through RIN results in higher dissipation for RIN and the LTC4253. An alternative is a separate NPN buffer driving the optocoupler as shown in Figure 3. Multiple 1/4W resistors can replace a single higher power RIN resistor. INTERNAL UNDERVOLTAGE LOCKOUT (UVLO) A hysteretic comparator, UVLO, monitors VIN for undervoltage. The thresholds are defined by VLKO and its hysteresis VLKH. When VIN rises above 9.2V (VLKO) the chip is enabled; below 8.2V (VLKO - VLKH) it is disabled and GATE is pulled low. The UVLO function at VIN should not be confused with the UV and OV pins. These are completely separate functions.
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reset by either pulling the RESET pin active high until TIMER goes low, pulling UV momentarily low, dropping the input voltage VIN below the internal UVLO threshold of 8.2V or pulsing TIMER momentarily low with a switch. Although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent protection. Noise spikes from the backplane or load, input steps caused by the connection of a second, higher voltage supply, transient currents caused by faults on adjacent circuit boards sharing the same power bus or the insertion of non-hot swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. The action of TIMER and CT rejects these events allowing the LTC4253 to "ride out" temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse.
(Refer to Block Diagram)
UV/OV COMPARATORS An UV hysteretic comparator detects undervoltage conditions at the UV pin, with the following thresholds: UV low-to-high (VUVHI) = 3.225V UV high-to low (VUVLO) = 2.925V An OV hysteretic comparator detects overvoltage conditions at the OV pin, with the following thresholds: OV low-to-high (VOVHI) = 6.150V OV high-to-low (VOVLO) = 5.850V The UV and OV trip point ratio is designed to match the standard telecom operating range of 43V to 75V when connected together as in Figure 2. A divider (R1, R2) is used to scale the supply voltage. Using R1 = 402k and R2 = 32.4k gives a typical operating range of 43.2V to 78.4V. The under and overvoltage shutdown thresholds are then 39.2V and 82.5V. One percent divider resistors are recommended to preserve threshold accuracy.
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LTC4253
APPLICATIO S I FOR ATIO
GND RIN 10k 20k(1/4W)/2 PUSH RESET GND SHORT PIN R1 432k 1% R2 14k 1% CIN 1F
R4 22k
4 VIN LTC4253 12 11 5 C1 10nF CSS 68nF 6 14 CSQ 0.1F 13 UV OV RESET PWRGD1 PWRGD2 PWRGD3 EN3 EN2 SS SQTIMER TIMER VEE 8 CT 0.33F CC 18nF DRAIN GATE SENSE 3 2 16 15 1 10 9 7 RC 10 RD 1M Q1 IRF530S VIN R8 POWER MODULE 1 OUTPUT EN2 EN3 VIN POWER MODULE 2 OUTPUT R9

R3 32.4k 1%
R10 47k
-48V
Figure 3. -48V/2.5A Application with Wider Operating Range
The R1-R2 divider values shown set a standing current of slightly more than 100A and define an impedance at UV/OV of 30k. In most applications, 30k impedance coupled with 300mV UV hysteresis makes the LTC4253 insensitive to noise. If more noise immunity is desired, add a 1nF to 10nF filter capacitor from UV/OV to VEE. The separate UV and OV pins can be used for wider operating range such as 35.5V to 80V range as shown in Figure 3. Other combinations are possible with different resistors arrangement. UV/OV OPERATION A low input to the UV comparator will reset the chip and pull the GATE and TIMER pins low. A low-to-high UV transition will initiate an initial timing sequence if the other interlock conditions are met. A high-to-low transition in the UV comparator immediately shuts down the LTC4253, pulls the MOSFET gate low and resets the three latched PWRGD signals high. An overvoltage condition is detected by the OV comparator and pulls GATE low, thereby shutting down the load, but it will not reset the circuit breaker TIMER and PWRGD flags. Returning from the overvoltage condition will
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Q2 FZT857 R5 2.2k R6 2.2k CL 100F R7 2.2k
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POWER MODULE 1 EN POWER MODULE 2 EN
POWER MODULE 3 EN
RS 0.02
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MOC207
restart the GATE pin if all the interlock conditions except TIMER are met. Only during the initial timing cycle does OV condition have an effect of resetting TIMER. DRAIN Connecting an external resistor, RD, to this dual function DRAIN pin allows VOUT (MOSFET drain-source voltage drop) sensing without it being damaged by large voltage transients. Below 6.15V, negligible pin leakage allows a DRAIN low comparator to detect VOUT less than 2.385V (VDRNL). This, together with the GATE low comparator, sets the PWRGD flag. When VOUT > VDRNCL (7V), the DRAIN pin is clamped at about 7V and the current flowing in RD is given by:
IDRN
VOUT - VDRNCL RD
(1)
This current is scaled up 8 times during a circuit breaker fault before being added to the nominal 200A. This accelerates the fault TIMER pull-up when the MOSFET's drain-source voltage exceeds 7V and effectively shortens the MOSFET heating duration.
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LTC4253
APPLICATIO S I FOR ATIO
TIMER
The operation of the TIMER pin is somewhat complex as it handles several key functions. A capacitor CT is used at TIMER to provide timing for the LTC4253. Four different charging and discharging modes are available at TIMER: 1. 5A slow charge; initial timing and shutdown cooling delay. 2. (200A + 8 * IDRN) fast charge; circuit breaker delay. 3. 5A slow discharge; circuit breaker "cool-off" and shutdown cooling. 4. Low impedance switch; resets the TIMER capacitor after an initial timing delay, in UVLO, in UV and in OV during initial timing and when RESET is high. For initial timing delay, the 5A pull-up is used. The low impedance switch is turned off and the 5A current source is enabled when the interlock conditions are met. CT charges to 4V in a time period given by:
4V * C T t= 5A
NORMALIZED RESPONSE TIME (s/F)
When CT reaches VTMRH ( 4V), the low impedance switch turns on and discharges CT. A GATE start-up cycle begins and both SS and GATE outputs are released. CIRCUIT BREAKER TIMER OPERATION If the SENSE pin detects more than 50mV drop across RS, the TIMER pin charges CT with (200A + 8 * IDRN). If CT charges to 4V, the GATE pin pulls low and the LTC4253 latches off. The LTC4253 remains latched off until the RESET pin is momentarily pulsed high, the UV pin is momentarily pulsed low, the TIMER pin is momentarily discharged low by an external switch or VIN dips below UVLO and is then restored. The circuit breaker timeout period is given by:
t=
4V * C T 200A + 8 * IDRN
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If VOUT < 6.15V, an internal PMOS isolates DRAIN pin leakage current and this makes IDRN = 0 in Equation (3). If VOUT is above 7V (VDRNCL) during the circuit breaker fault period, the charging of CT is accelerated by 8 * IDRN of Equation (1). Intermittent overloads may exceed the 50mV threshold at SENSE but, if their duration is sufficiently short, TIMER will not reach 4V and the LTC4253 will not shut the external MOSFET off. To handle this situation, the TIMER discharges CT slowly with a 5A pull-down whenever the SENSE voltage is less than 50mV. Therefore any intermittent overload with VOUT < 6.15V and an aggregate duty cycle of 2.5% or more will eventually trip the circuit breaker and shut down the LTC4253. Figure 4 shows the circuit breaker response time in seconds normalized to 1F. The asymmetric charging and discharging of CT is a fair gauge of MOSFET heating. The normalized circuit response time is estimated by:
t 4 = C T (F ) (200 + 8 * IDRN ) * D - 5
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[
]
(4)
10
1
0.1
4 t = CT(F) (200 + 8 * IDRN) * D - 5
0.01
0
20 40 60 80 FAULT DUTY CYCLE, D (%)
100
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Figure 4. Circuit Breaker Response Time
(3)
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APPLICATIO S I FOR ATIO
POWER GOOD SEQUENCING
After the initial TIMER cycle, GATE ramps up to turn on the external MOSFET which in turn pulls DRAIN low. When GATE is within 2.8V of VIN and DRAIN is lower than VDRNL, the power good sequence starts with PWRGD1 pulling active low. This starts off a 5A pull-up on the SQTIMER pin which ramps up until it reaches the 4V threshold then pulls low. When the SQTIMER pin floats, this delay tSQT is about 300s. Connecting an external capacitor CSQ from SQTIMER to VEE modifies the delay to:
tSQT =
4V * C SQ 5A
PWRGD2 asserts when EN2 goes high and PWRGD1 has asserted for more than one tSQT. When PWRGD2 successfully pulls low, SQTIMER ramps up on another delay cycle. PWRGD3 asserts when EN2 and EN3 go high and PWRGD2 has asserted for more than one tSQT. All three PWRGD signals are reset in UVLO, in UV condition, if RESET is high or when CT charges up to 4V. In addition, PWRGD2 is reset by EN2 going low. PWRGD3 is reset by EN2 or EN3 going low. An overvoltage condition has no effect on the PWRGD flags. A 50A current pulls each PWRGD pin high when reset. As power modules signal common are different from PWRGD, optoisolation is recommended. These three pins can sink an optodiode current. Figure 18 shows an NPN configuration for the PWRGD interface. A limiting base resistor should be used for each NPN and the module enable input should have protection from negative bias current. SOFT-START Soft-start is effective in limiting the inrush current during GATE start-up. Unduly long soft-start intervals can exceed the MOSFET's SOA duration if powering-up into an active load. When the SS pin floats, an internal current source ramps SS from 0V to 2.2V in about 300s. Connecting an external capacitor, CSS, from SS to ground modifies the ramp to approximate an RC response of:
-t RSSC SS VSS (t) VSS 1 - e
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An internal resistor divider (95k/5k) scales VSS(t) down by 20 times to give the analog current limit threshold: VACL ( t) = VSS( t) - VOS 20 (7) This allows the inrush current to be limited to VACL(t)/RS. The offset voltage, VOS (10mV) ensures CSS is sufficiently discharged and the ACL amplifier is in current limit mode before GATE start-up. SS is discharged low during UVLO at VIN , UV, OV, during the initial timing cycle, a latched circuit breaker fault or the RESET pin going high. GATE GATE is pulled low to VEE under any of the following conditions: in UVLO, when RESET pulls high, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or a latched circuit breaker fault. When GATE turns on, a 50A current source charges the MOSFET gate and any associated external capacitance. VIN limits the gate drive to no more than 14.5V. Gate-drain capacitance (CGD) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the MOSFET. A unique circuit pulls GATE low with practically no usable voltage at VIN, and eliminates current spikes at insertion. A large external gate-source capacitor is thus unnecessary for the purpose of compensating CGD. Instead, a smaller value (10nF) capacitor CC is adequate. CC also provides compensation for the analog current limit loop. GATE has two comparators: the GATE low comparator looks for < 0.5V threshold prior to initial timing; the GATE high comparator looks for < 2.8V relative to VIN and, together with DRAIN low comparator, sets PWRGD1 output during GATE startup. SENSE The SENSE pin is monitored by the circuit breaker (CB) comparator, the analog current limit (ACL) amplifier, and the fast current limit (FCL) comparator. Each of these three measures the potential of SENSE relative to VEE. When SENSE exceeds 50mV, the CB comparator activates the 200A TIMER pull-up. At 100mV the ACL amplifier servos the MOSFET current, and at 200mV the FCL comparator
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(6)
LTC4253
APPLICATIO S I FOR ATIO
abruptly pulls GATE low in an attempt to bring the MOSFET current under control. If any of these conditions persists long enough for TIMER to charge CT to 4V (see Equation 3), the LTC4253 shuts down and pulls GATE low. If the SENSE pin encounters a voltage greater than 100mV, the ACL amplifier will servo GATE downwards in an attempt to control the MOSFET current. Since GATE overdrives the MOSFET in normal operation, the ACL amplifier needs time to discharge GATE to the threshold of the MOSFET. For a mild overload the ACL amplifier can control the MOSFET current, but in the event of a severe overload the current may overshoot. At SENSE = 200mV the FCL comparator takes over, quickly discharging the GATE pin to near VEE potential. FCL then releases, and the ACL amplifier takes over. All the while TIMER is running. The effect of FCL is to add a nonlinear response to the control loop in favor of reducing MOSFET current. Owing to inductive effects in the system, FCL typically overcorrects the current limit loop, and GATE undershoots. A zero in the loop (resistor RC in series with the gate capacitor) helps the ACL amplifier to recover. SHORT-CIRCUIT OPERATION Circuit behavior arising from a load side low impedance short is shown in Figure 5. Initially the current overshoots the analog current limit level of VSENSE = 200mV (trace 2) as the GATE pin works to bring VGS under control (trace 3). The overshoot glitches the backplane in the negative direction and when the current is reduced to 100mV/RS, the backplane responds by glitching in the positive direction. TIMER commences charging CT (trace 4) while the analog current limit loop maintains the fault current at 100mV/RS, which in this case is 5A (trace 2). Note that the backplane voltage (trace 1) sags under load. Timer pull-up is accelerated by VOUT. When CT reaches 4V, GATE turns off, the PWRGD signal pulls high, the load current drops to zero and the backplane rings up to over 100V. The positive peak is usually limited by avalanche breakdown in the MOSFET, and can be further limited by adding a zener diode (such as Diodes Inc. SMAT70A) across the input from - 48V to - 48RTN. A low impedance short on one card may influence the behavior of others sharing the same backplane. The initial
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glitch and backplane sag as seen in Figure 5 trace 1, can rob charge from output capacitors on the adjacent card. When the faulty card shuts down, current flows in to refresh the capacitors. If LTC4253s are used by the other cards, they respond by limiting the inrush current to a value of 100mV/RS. If CT is sized correctly, the capacitors will recharge long before CT times out.
SUPPLY RING OWING TO CURRENT OVERSHOOT SUPPLY RING OWING TO MOSFET TURN-OFF
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-48RTN 0.5ms 50V SENSE 0.5ms 200mV GATE 0.5ms 10V
TIMER
TRACE 1
ONSET OF OUTPUT SHORT-CIRCUIT
TRACE 2
FAST CURRENT LIMIT ANALOG CURRENT LIMIT CTIMER RAMP LATCH OFF
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TRACE 3
0.5ms 5V
TRACE 4
Figure 5. Output Short-Circuit Behavior of LTC4253
MOSFET SELECTION The external MOSFET switch must have adequate safe operating area (SOA) to handle short-circuit conditions until TIMER times out. These considerations take precedence over DC current ratings. A MOSFET with adequate SOA for a given application can always handle the required current but the opposite may not be true. Consult the manufacturer's MOSFET datasheet for safe operating area and effective transient thermal impedance curves. MOSFET selection is a 3-step process by assuming the absense of soft-start capacitor. First, RS is calculated and then the time required to charge the load capacitance is determined. This timing, along with the maximum shortcircuit current and maximum input voltage, defines an operating point that is checked against the MOSFET's SOA curve. To begin a design, first specify the required load current and Ioad capacitance, IL and CL. The circuit breaker current trip point (VCB/RS) should be set to accommodate the maximum load current. Note that maximum input current to a DC/DC converter is expected at VSUPPLY(MIN). RS is given by: 4253fa
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LTC4253
APPLICATIO S I FOR ATIO
RS = VCB(MIN) IL(MAX)
where VCB(MIN) = 40mV represents the guaranteed minimum circuit breaker threshold. During the initial charging process, the LTC4253 may operate the MOSFET in current limit, forcing (VACL) between 80mV to 120mV across RS. The minimum inrush current is given by:
80mV IINRUSH(MIN)= RS
Maximum short-circuit current limit is calculated using the maximum VSENSE. This gives
ISHORTCIRCUIT(MAX) = 120mV RS
The TIMER capacitor CT must be selected based on the slowest expected charging rate; otherwise TIMER might time out before the load capacitor is fully charged. A value for CT is calculated based on the maximum time it takes the load capacitor to charge. That time is given by:
tCL(CHARGE) =
C * V C L * VSUPPLY(MAX) = I IINRUSH(MIN)
The maximum current flowing in the DRAIN pin is given by: IDRN(MAX) = VSUPPLY(MAX) - VDRNCL RD (12)
Approximating a linear charging rate, IDRN drops from IDRN(MAX) to zero, the IDRN component in Equation (3) can be approximated with 0.5 * IDRN(MAX). Rearranging the equation, TIMER capacitor CT is given by:
CT =
tCL(CHARGE) * (200A + 4 * IDRN(MAX) ) 4V
Returning to Equation (3), the TIMER period is calculated and used in conjunction with V SUPPLY(MAX) and ISHORTCIRCUIT(MAX) to check the SOA curves of a prospective MOSFET.
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(8) As a numerical design example, consider a 30W load, which requires 1A input current at 36V. If VSUPPLY(MAX) = 72V and CL = 100F, RD = 1M, Equation (8) gives RS = 40m; Equation (13) gives CT = 441nF. To account for errors in RS, CT, TIMER current (200A), TIMER threshold (4V), RD, DRAIN current multiplier and DRAIN voltage clamp (VDRNCL), the calculated value should be multiplied by 1.5, giving the nearest standard value of CT = 680nF. If a short-circuit occurs, a current of up to 120mV/40m = 3A will flow in the MOSFET for 3.6ms as dictated by CT = 680nF in Equation (3). The MOSFET must be selected based on this criterion. The IRF530S can handle 100V and 3A for 10ms and is safe to use in this application. Computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear MOSFET's SOA characteristics and the RSSCSS response. An overconservative but simple approach begins with the maximum circuit breaker current, given by: (9) (10)
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ICB(MAX) =
60mV RS
(14)
(11)
From the SOA curves of a prospective MOSFET, determine the time allowed, tSOA(MAX). CSS is given by: C SS = tSOA(MAX) 0.916 * RSS (15)
In the above example, 60mV/40m gives 1.5A. tSOA for the IRF530S is 40ms. From Equation (15), CSS = 437nF. Actual board evaluation showed that CSS = 100nF was appropriate. The ratio ( RSS * CSS ) to tCL(CHARGE) is a good gauge as large ratios may result in the time-out period expiring prematurely. This gauge is determined empirically with board level evaluation. SUMMARY OF DESIGN FLOW To summarize the design flow, consider the application shown in Figure 2. It was designed for 50W and CL = 100F.
(13)
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APPLICATIO S I FOR ATIO
Calculate RS: from Equation (8) RS = 20m.
Calculate maximum load current: 50W/36V = 1.4A; allowing for 83% converter efficiency, IIN(MAX) = 1.7A. Calculate I SHORT-CIRCUIT(MAX) : from Equation (10) ISHORTCIRCUIT(MAX) = 6A. Select a MOSFET that can handle 6A at 72V: IRF530S. Calculate CT: from Equation (13) CT = 220nF. Select CT = 330nF, which gives the circuit breaker time-out period tMAX = 1.76ms. Consult MOSFET SOA curves: the IRF530S can handle 6A at 72V for 5ms, so it is safe to use in this application. Calculate CSS: using Equations (14) and (15) select CSS = 68nF. FREQUENCY COMPENSATION The LTC4253 typical frequency compensation network for the analog current limit loop is a series RC (10) and CC connected from GATE to VEE. Figure 6 depicts the relationship between the compensation capacitor CC and the MOSFET's CISS. The line in Figure 6 is used to select a starting value for CC based upon the MOSFET's CISS specification. Optimized values for CC are shown for several popular MOSFETs. Differences in the optimized value of CC versus the starting value are small. Nevertheless, compensation values should be verified by board level short-circuit testing.
60 COMPENSATION CAPACITOR CC (nF) 50 40 30 20 10 0 IRF540 IRF530 IRF740 NTY100N10
IRF3710
0
2000
6000 4000 MOSFET CISS (pF)
8000
4253 F06
Figure 6. Recommended Compensation Capacitor CC vs MOSFET CISS
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As seen in Figure 5, at the onset of a short-circuit event, the input supply voltage can ring dramatically due to series inductance. If this voltage avalanches the MOSFET, current continues to flow through the MOSFET to the output. The analog current limit loop cannot control this current flow and therefore the loop undershoots. This effect cannot be eliminated by frequency compensation. A zener diode is required to clamp the input supply voltage and prevent MOSFET avalanche. SENSE RESISTOR CONSIDERATIONS For proper circuit breaker operation, Kelvin-sense PCB connections between the sense resistor and the LTC4253's VEE and SENSE pins are strongly recommended. The drawing in Figure 7 illustrates the correct way of making connections between the LTC4253 and the sense resistor. PCB layout should be balanced and symmetrical to minimize wiring errors. In addition, the PCB layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. TIMING WAVEFORMS System Power-Up Figure 8 details the timing waveforms for a typical powerup sequence in the case where a board is already installed in the backplane and system power is applied abruptly. At
CURRENT FLOW FROM LOAD CURRENT FLOW TO -48V BACKPLANE SENSE RESISTOR TRACK WIDTH W: 0.03" PER AMP ON 1 OZ COPPER W
4253 F07
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TO SENSE
TO VEE
Figure 7. Making PCB Connections to the Sense Resistor
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APPLICATIO S I FOR ATIO
time point 1, the supply ramps up, together with UV/OV, VOUT and DRAIN. VIN and the PWRGD signals follow at a slower rate as set by the VIN bypass capacitor. At time point 2, VIN exceeds VLKO and the internal logic checks for UV > VUVHI, OV < VOVLO, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS, and TIMER < VTMRL. When all conditions are met, initial timing starts and the TIMER capacitor is charged by a 5A current source pull-up. At
VIN CLEARS VLKO, CHECK UV > VUVHI, OV < VOVLO, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 12 GND - VEE OR (-48RTN) - (-48V) 3 4 56 7 89 A B C D
UV/OV
VIN
VLKO VTMRH 5A VTMRL 50A 50A 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL VCB 200A + 8 * IDRN 5A VIN - VGATEH 5A
TIMER
GATE
VGATEL
SS
SENSE VOUT
DRAIN 50A PWRGD1
PWRGD2
PWRGD3 VSQTMRH SQTIMER 5A 5A VSQTMRH
EN2
EN3 GATE START-UP
INITIAL TIMING
Figure 8. System Power-Up Timing (All Waveforms are Referenced to VEE)
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time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < VGATEL, SENSE < VCB and SS < 20 * VOS must be satisfied before the GATE startup cycle begins. SS ramps up as dictated by RSS * CSS (as in Equation 6); GATE is held low by the analog current limit (ACL) amplifier until SS crosses 20 * VOS. Upon releasing
VDRNCL VDRNL VIH VIH
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APPLICATIO S I FOR ATIO
GATE, 50A sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET's threshold, current flows into the load capacitor at time point 5. At time point 6, load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed, the SENSE voltage is regulated at VACL(t) (equation 7) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE - VEE) reaches the VCB threshold at time point 7, circuit breaker TIMER activates. The TIMER capacitor, CT is charged by a (200A + 8 * IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At time point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB, the fault TIMER ends, followed by a 5A discharge cycle (cool-off). The duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid fault time-out during GATE rampup. When GATE ramps past the VGATEH threshold at time point A, PWRGD1 pulls low. At time point B, GATE reaches its maximum voltage as determined by VIN. At time point A, SQTIMER starts its ramp-up to 4V. Having satisfied the requirement that PWRGD1 is low for more than one tSQT, PWRGD2 pulls low after EN2 pulls high above the VIH threshold at time point C. This sets off the second SQTIMER ramp-up. Having satisfied the requirement that PWRGD2 is low for more than one tSQT, PWRGD3 pulls low after EN3 pulls high at time point D. Live Insertion with Short Pin Control of UV/OV In the example shown in Figure 9, power is delivered through long connector pins whereas the UV/OV divider makes contact through a short pin. This ensures the power connections are firmly established before the LTC4253 is activated. At time point 1, the power pins make contact and VIN ramps through VLKO. At time point 2, the UV/OV divider makes contact and its voltage exceeds VUVHI. In addition, the internal logic checks for OV < VOVHI, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS and TIMER < VTMRL. When all conditions are met, initial timing starts and the
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TIMER capacitor is charged by a 5A current source pullup. At time point 3, TIMER reaches the VTMRH threshold and the initial timing cycle terminates. The TIMER capacitor is quickly discharged. At time point 4, the VTMRL threshold is reached and the conditions of GATE < V GATEL, SENSE < VCB and SS < 20 * VOS must be satisfied before the GATE start-up cycle begins. SS ramps up as dictated by RSS * CSS; GATE is held low by the analog current limit amplifier until SS crosses 20 * VOS. Upon releasing GATE, 50A sources into the external MOSFET gate and compensation network. When the GATE voltage reaches the MOSFET's threshold, current begins flowing into the load capacitor at time point 5. At time point 6, load current reaches SS control level and the analog current limit loop activates. Between time points 6 and 8, the GATE voltage is servoed and the SENSE voltage is regulated at VACL(t) and soft-start limits the slew rate of the load current. If the SENSE voltage (VSENSE - VEE) reaches the VCB threshold at time point 7, the circuit breaker TIMER activates. The TIMER capacitor, CT is charged by a (200A + 8 * IDRN) current pull-up. As the load capacitor nears full charge, load current begins to decline. At point 8, the load current falls and the SENSE voltage drops below VACL(t). The analog current limit loop shuts off and the GATE pin ramps further. At time point 9, the SENSE voltage drops below VCB and the fault TIMER ends, followed by a 5A discharge current source (cool-off). When GATE ramps past VGATEH threshold at time point A, PWRGD1 pulls low, starting off the PWRGD sequence. PWRGD2 pulls low at time point C when EN2 is high and PWRGD1 is low for more than one tSQT. PWRGD3 pulls low at time point D when EN2 and EN3 is high and PWRGD2 is low for more than one tSQT. At time point B, GATE reaches its maximum voltage as determined by VIN. Undervoltage Timing In Figure 10 when the UV pin drops below VUVLO (time point 1), the LTC4253 shuts down with TIMER, SS and GATE pulled low. If current has been flowing, the SENSE pin voltage decreases to zero as GATE collapses. When UV recovers and clears VUVHI (time point 2), an initial time cycle begins followed by a start-up cycle.
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LTC4253
APPLICATIO S I FOR ATIO
1 GND - VEE OR (-48RTN) - (-48V) 2
UV CLEARS VUVHI, CHECK OV < VOVHI, RESET = 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 3 456 7 89 A B C D
UV/OV
VUVHI
VIN
VLKO VTMRH 200A + 8 * IDRN 5A 50A 5A
TIMER
5A VTMRL
GATE
VGATEL 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS
SS
SENSE VOUT
DRAIN 50A PWRGD1
PWRGD2
PWRGD3 VSQTMRH SQTIMER 5A 5A VSQTMRH VSQTMRL
EN2
EN3 INITIAL TIMING GATE START-UP
4253 F09
Figure 9. Power-Up Timing with a Short Pin (All Waveforms are Referenced to VEE)
VIN Undervoltage Lockout Timing VIN undervoltage lockout comparator, UVLO has a similar timing behaviour as the UV pin timing except it looks at VIN for (VLKO - VLKH) to shut down and VLKO to revive. In VIN shutdown, both UV and OV comparators are preset off. This effectively causes the UV comparator to look for VUVHI threshold and OV comparator to look for VOVLO threshold when VIN comes out of undervoltage lockout. Undervoltage Timing with Overvoltage Glitch In Figure 11, both UV and OV pins are connected together, clears VUVHI (time point 1), an initial timing cycle starts. If the system bus voltage overshoots VOVHI as shown at time
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50A VIN - VGATEH VACL VCB VDRNCL VDRNL VSQTMRL
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point 2, TIMER discharges. At time point 3, the supply voltage recovers and drops below the VOVLO threshold. The initial timing cycle restarts and is followed by a GATE start-up cycle. Overvoltage Timing During normal operation, if the OV pin exceeds VOVHI as shown at time point 1 of Figure 12, the TIMER and PWRGD status are unaffected; SS and GATE pull down; load disconnects. At time point 2, OV recovers and drops below the VOVLO threshold; GATE start-up begins. If the overvoltage glitch is long enough to deplete the load capacitor, time points 4 through 7 may occur.
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APPLICATIO S I FOR ATIO
UV DROPS BELOW VUVLO. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES UV CLEARS VUVHI, CHECK OV CONDITION, RESET < 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 UV 2 VUVHI VTMRH TIMER 5A VTMRL 50A GATE VGATEL 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN 50A PWRGD1 VDRNL 50A 3 4 56 7 89 A B C D
VUVLO
SS
PWRGD2
PWRGD3 VSQTMRH SQTIMER 5A VSQTMRL EN2 5A VSQTMRH VSQTMRL
EN3 GATE START-UP
INITIAL TIMING
Figure 10. Undervoltage Timing (All Waveforms are Referenced to VEE)
Circuit Breaker Timing In Figure 13a, the TIMER capacitor charges at 200A if the SENSE pin exceeds VCB but VDRN is less than 6.15V. If the SENSE pin returns below VCB before TIMER reaches the VTMRH threshold, TIMER is discharged by 5A. In Figure 13b, when TIMER exceeds VTMRH, GATE pulls down immediately and the chip shuts down. In Figure 13c, multiple momentary faults cause the TIMER capacitor to integrate and reach VTMRH followed by GATE pull down and the chip shuts down. During chip shutdown, LTC4253 latches TIMER high with a 5A pull-up current source.
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200A + 8 * IDRN 5A 5A VIN - VGATEH
4253 F10
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Resetting a Fault Latch A latched circuit breaker fault of the LTC4253 has the benefit of a long cooling time. The latched fault can be reset by pulsing the RESET pin high until the TIMER pin is pulled below VTMRL( 1V ) as shown in Figure 14. After the RESET pulse, SS and GATE ramp up without an initial timing cycle provided the interlock conditions are satisfied. Alternative methods of reset include using an external switch to pulse the UV pin below VUVLO or the VIN pin
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APPLICATIO S I FOR ATIO
below (VLKO - VLKH). Pulling the TIMER pin below VTMRL and the SS pin to 0V then simultaneously releasing them also achieves a reset. An initial timing cycle is generated for reset by pulsing the UV pin or VIN pin, while no initial timing cycle is generated for reset by pulsing of the TIMER and SS pins. Using Reset as an ON/OFF switch The asynchronous RESET pin can be used as an on/off function to cut off supply to the external power modules or loads controlled by the chip. Pulling RESET high will pull
UV/OV CLEARS VUVHI, CHECK OV CONDITION, RESET< 0.8V, GATE < VGATEL, SENSE < VCB, SS < 20 * VOS AND TIMER < VTMRL UV/OV OVERSHOOTS VOVHI AND TIMER ABORTS INITIAL TIMING CYCLE UV/OV DROPS BELOW VOVLO AND TIMER RESTARTS INITIAL TIMING CYCLE TIMER CLEARS VTMRL, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 VOVHI UV/OV VUVHI VTMRH TIMER 5A VTMRL 50A GATE VGATEL 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN 50A PWRGD1 VDRNL 50A 200A + 8 * IDRN 5A 5A VIN - VGATEH 2 3 VOVLO 4 5 67 8 9A B C D E
SS
PWRGD2
PWRGD3 VSQTMRH SQTIMER 5A VSQTMRL EN2 5A VSQTMRH VSQTMRL
EN3 GATE START-UP
INITIAL TIMING
Figure 11. Undervoltage Timing with an Overvoltage Glitch (All Waveforms are Referenced to VEE)
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GATE, SS, TIMER and SQTIMER low and the PWRGD signal high. The supply is fully cut off if the RESET pulse is maintained wide enough to fully discharge the GATE and SS pins. As long as RESET is high, GATE, SS, TIMER and SQTIMER are strapped to VEE and the supply is cut off. When RESET is released, if VSENSE > VCB, UV < VUVLO, OV > VOVHI or VIN is in UVLO, the chip waits for the interlock conditions before recovering as described in the Operation, Interlock Conditions section. If not, the GATE pin will ramp up in a soft start cycle without going through an initial cycle.
4253 F11
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LTC4253
APPLICATIO S I FOR ATIO
Analog Current Limit and Fast Current Limit
In Figure 15a, when SENSE exceeds VACL, GATE is regulated by the analog current limit amplifier loop. When SENSE drops below VACL, GATE is allowed to pull up. In Figure 15b, when a severe fault occurs, SENSE exceeds VFCL and GATE immediately pulls down until the analog current amplifier establishes control. If the severe fault
OV OVERSHOOTS VOVHI. GATE AND SS ARE PULLED DOWN, PWRGD SIGNALS AND TIMER ARE UNAFFECTED OV DROPS BELOW VOVLO, CHECK GATE < VGATEL, SENSE < VCB AND SS < 20 * VOS 1 VOVHI 2 34 5 67 8 9
OV
VOVLO VTMRH
TIMER
200A + 8 * IDRN
GATE VGATEL
50A
20 * (VACL + VOS) SS 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB GATE START-UP
Figure 12. Overvoltage Timing (All Waveforms are Referenced to VEE)
CB TIMES-OUT 1 200A + 8 * IDRN TIMER 2 VTMRH 5A 1 VTMRH 200A + 8 * IDRN TIMER 2 CB TIMES-OUT 1 2 3 VTMRH 200A + 8 * IDRN TIMER 5A 4
GATE
SS VACL SENSE VOUT VCB
DRAIN
PWRGD1
CB FAULT
(13a) Momentary Circuit Breaker Fault
Figure 13. Circuit Breaker Timing Behavior (All Waveforms are Referenced to VEE)
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causes VOUT to exceed VDRNCL, the DRAIN pin is clamped at VDRNCL. IDRN flows into the DRAIN pin and is multiplied by 8. This extra current is added to the TIMER pull-up current of 200A. This accelerated TIMER current of (200A + 8 * IDRN) produces a shorter circuit breaker fault delay. Careful selection of CT, RD and MOSFET helps prevent SOA damage in a low impedance fault condition.
5A 5A 50A VIN - VGATEH
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GATE
GATE
SS VACL SENSE VOUT VDRNCL DRAIN VCB
SS VACL SENSE VOUT VDRNCL DRAIN VCB
PWRGD1
PWRGD1
CB FAULT
CB FAULT
CB FAULT
4253 F13
(13b) Circuit Breaker Time-Out
(13c) Multiple Circuit Breaker Fault
27
LTC4253
APPLICATIO S I FOR ATIO
Soft-Start
If the SS pin is not connected, this pin defaults to a linear voltage ramp, from 0V to 2.2V in about 300s at GATE start-up, as shown in Figure 16a. If a soft-start capacitor, CSS, is connected to this SS pin, the soft-start response is modified from a linear ramp to an RC response (Equation 6), as shown in Figure 16b. This feature allows load current to slowly ramp-up at GATE start-up. Softstart is initiated at time point 3 by a TIMER transition from VTMRH to VTMRL (time points 1 and 2) or by the OV pin falling below the VOVLO threshold after an OV condition. When the SS pin is below 0.2V, the analog current limit amplifier keeps GATE low. Above 0.2V, GATE is released and 50A ramps up the compensation network and GATE
LATCHED TIMER RESET BY RESET PULLING HIGH RESET PULLS LOW 1 5A TIMER VTMRL 50A VGATEL 50A VIN - VGATEH VTMRH 200A + 8 * IDRN 5A 5A 2 34 5 67 8 9
GATE
20 * (VACL + VOS) SS 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN 50A VDRNL
PWRGD1
RESET
VIH VIL RESET PULSE WIDTH MUST FULLY DISCHARGE TIMER
Figure 14. Reset of LTC4253's Latched Fault (All Waveforms are Referenced to VEE)
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capacitance at time point 4. Meanwhile, the SS pin voltage continues to ramp up. When GATE reaches the MOSFET's threshold, the MOSFET begins to conduct. Due to the MOSFET's high gm, the MOSFET current quickly reaches the soft-start control value of VACL(t) (Equation 7). At time point 6, the GATE voltage is controlled by the current limit amplifier. The soft-start control voltage reaches the circuit breaker voltage, VCB at time point 7 and the circuit breaker TIMER activates. As the load capacitor nears full charge, load current begins to decline below VACL(t). The current limit loop shuts off and GATE releases at time point 8. At time point 9, SENSE voltage falls below VCB and TIMER deactivates.
4253 F14
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LTC4253
APPLICATIO S I FOR ATIO
Large values of CSS can cause premature circuit breaker time-out as VACL(t) may marginally exceed the VCB potential during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A more serious side effect of a large CSS value is that SOA duration may be exceeded during soft-start into a low impedance load. A soft-start voltage below VCB will not activate the circuit breaker TIMER. Power Limit Circuit Breaker Figure 17 shows the LTC4253 in a power limit circuit breaking application. The SENSE pin is modulated by board voltage VSUPPLY. The zener voltage, VZ of D1, is set to be the same as the lowest operating voltage, VSUPPLY(MIN) = 36V. If the goal is to have the high supply operating voltage, VSUPPLY(MAX) = 72V give the same power as available at VSUPPLY(MIN), then resistors R3 and R7 are selected by:
R7 VCB = R3 VSUPPLY(MAX)
12 VTMRH 200A + 8 * IDRN TIMER GATE 34 5A
SS VACL SENSE VCB SENSE
VOUT
DRAIN
PWRGD1
(15a) Analog Current Limit Fault
Figure 15. Current Limit Behavior (All Waveforms are Referenced to VEE)
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If R7 is 22, then R3 is 31.6k. The peak circuit breaker power limit is:
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(VSUPPLY(MIN) + VSUPPLY(MAX) )2 POWER(MAX) =
4 * VSUPPLY(MIN) * VSUPPLY(MAX) * POWER AT VSUPPLY(MIN) = 1.125 * POWER AT VSUPPLY(MIN)
(17)
when VSUPPLY = 0.5 * (VSUPPLY(MIN) + VSUPPLY(MAX)) = 54V The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is:
POWER(FAULT ) =
(VSUPPLY ) * V
RS
ACL
- (VSUPPLY - VZ )*
R7 R3
(18)
(16)
CB TIMES-OUT 1 VTMRH 200A + 8 * IDRN TIMER GATE 2
VFCL VACL VCB
VOUT VDRNCL DRAIN
PWRGD1
4253 F15
(15b) Fast Current Limit Fault
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LTC4253
APPLICATIO S I FOR ATIO
END OF INITIAL TIMING CYCLE 12 3 4 5 6 7 VTMRH TIMER VTMRL 200A + 8 * IDRN 7a 89 10
5A TIMER VTMRL 50A
GATE VGS(th) 50A
20 * (VACL + VOS) SS 20 * (VCB + VOS) 20 * VOS VACL SENSE VCB VDRNCL DRAIN 50A PWRGD1 PWRGD1 VDRNL DRAIN SENSE SS
(16a) Without External CSS
Figure 16. Soft-Start Timing (All Waveforms are Referenced to VEE)
GND
RIN 2.8k 16k(1/4W)/6
VIN CIN 1F
R3 31.6k R4 5.6k R5 5.6k
D1 BZX84C36
GND SHORT PIN R1 402k 1%
4 VIN LTC4253 11 12 5 C1 10nF CSS 68nF 6 14 CSQ 0.1F 13 OV UV RESET PWRGD1 PWRGD2 PWRGD3 EN3 EN2 SS SQTIMER TIMER VEE 8 CT 0.33F DRAIN GATE SENSE 3 2 16 15 1 10 9 7
RESET
R2 32.4k 1%
R7 22 CC 18nF
-VSUPPLY
Figure 17. Power Limit Circuit Breaker Application
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END OF INITIAL TIMING CYCLE 11 12 3 4 5 6 VTMRH 200A + 8 * IDRN 5A 7 89 10 11 50A VIN - VGATEH GATE VGS(th) 50A 20 * (VACL + VOS) 20 * (VCB + VOS) 20 * VOS VACL VCB VDRNCL VDRNL 50A VIN - VGATEH
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(16b) With External CSS
C2 100F R6 5.6k
+
C3 0.1F POWER MODULE 1 EN POWER MODULE 2 EN
POWER MODULE 3 EN
EN3 EN2 RD 1M Q1 IRF530S RC 10 RS 0.02 VIN R8 POWER MODULE 1 OUTPUT VIN
POWER MODULE 2 OUTPUT R9
MOC207
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LTC4253
APPLICATIO S I FOR ATIO
- 48V RTN (LONG PIN) RIN 2.8k 16k(1/4W)/6
- 48V RTN (SHORT PIN)
R1 402k 1%
4 11
1
CIN 1F 15 3 2
VIN EN2 EN3 OV 12 UV PWRGD1 PWRGD2 PWRGD3
RESET R2 32.4k 1% C1 10nF CSS 68nF
5 RESET
LTC4253 6 14 SS SQTIMER TIMER VEE CT 0.33F 8 CC 18nF DRAIN GATE SENSE 10 9 7 RC 10 RD 1M Q1 IRF530S RS 0.02 *DIODES, INC. FMMT493
B3100* - 48V A (LONG PINS) - 48V B B3100*
CSQ 0.1F
13
Figure 18. Transistor Enabled Sequencing Without Feedback
PACKAGE DESCRIPTIO
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.045 .005 .189 - .196* (4.801 - 4.978) 16 15 14 13 12 11 10 9
.254 MIN
.150 - .165 .229 - .244 (5.817 - 6.198) .150 - .157** (3.810 - 3.988)
.0165 .0015
.0250 TYP 1 .015 .004 x 45 (0.38 0.10) .053 - .068 (1.351 - 1.727) 23 4 56 7 8 .004 - .0098 (0.102 - 0.249)
RECOMMENDED SOLDER PAD LAYOUT
.007 - .0098 (0.178 - 0.249) .016 - .050 (0.406 - 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS)
0 - 8 TYP
3. DRAWING NOT TO SCALE *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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VIN R3 100k

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C2 100F C3 0.1F
R4 100k
R5 100k
POWER MODULE 1 EN
POWER MODULE 2 EN
POWER MODULE 3 EN
16
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.009 (0.229) REF
.008 - .012 (0.203 - 0.305)
.0250 (0.635) BSC
GN16 (SSOP) 0502
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LTC4253
TYPICAL APPLICATIO
GND RIN 2.8k 16k(1/4W)/6 PUSH RESET GND SHORT PIN R1 402k 1%
4
1
VIN EN2 EN3 11 12 5 C1 10nF CSS 27nF 6 14 CSQ 0.1F 13 SS SQTIMER TIMER VEE CT 150nF DRAIN GATE SENSE 10 9 7 R9 22 CC 22nF OV UV RESET PWRGD1 PWRGD2 PWRGD3 3 2 16
RESET
LTC4253 RD 1M
4253 F19
R2 32.4k 1%
R8 47k
-48V
Figure 19. - 48V/5A Application Sequenced Without Optical Feedback
RELATED PARTS
PART NUMBER LT1640AH/LT1640AL LT1641-1/LT1641-2 LTC1642 LT4250 LTC4251/LTC4251-1 LTC4251-2 LTC4252-1/LTC4252-2 DESCRIPTION Negative High Voltage Hot Swap Controllers in SO-8 Positive High Voltage Hot Swap Controllers in SO-8 Fault Protected Hot Swap Controller - 48V Hot Swap Controller - 48V Hot Swap Controllers in SOT-23 - 48V Hot Swap Controllers in MS8/MS10 COMMENTS Negative High Voltage Supplies from -10V to -80V Supplies from 9V to 80V, Autoretry/Latched Off 3V to 16.5V, Overvoltage Protection up to 33V Active Current Limiting, Supplies from - 20V to - 80V Fast Active Current Limiting, Supplies from - 15V Fast Active Current Limiting, Supplies from - 15V, Drain Accelerated Response
32
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
VIN CIN 1F R3 5.6k R4 5.6k C2 100F R5 5.6k
+
C3 0.1F POWER MODULE 1 EN POWER MODULE 2 EN
POWER MODULE 3 EN
15

Q1 IRF540S RC 10
RS 0.01
MOC207
4253fa LT/TP 0603 1K REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2002

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